This invention is related to threshold decoding, and more particularly to analog threshold decoding.
Conventionally, the output of a demodulator is a binary quantity which is set to a 1 or a 0 depending upon whether or not the demodulator wave form exceeds a predetermined decision level. Such binary or "hard" decisions ignore useful probability information which is present in the received signal, thus reducing the possible gain of the coding method.
Threshold decoders are typically separated into two different types, a Type I decoder which develops d.sub.m -1 parity checks on a single output estimate, where d.sub.m is the minimum distance of the code, and a Type II decoder which produces d.sub.m estimates of each output bit from which to make a majority decision.
FIG. 1 illustrates a typical Type I hard-decision decoder which contains a replica of the encoder used to recalculate parity bits from the received information (Y). The recalculated parity sequence is compared to the received parity sequence (Z) and the resulting syndrome pattern is stored in a shift register 2. The contents of the syndrome register are used to form the parity checks, with a majority decision of the parity checks determining whether or not an output bit is to be corrected. If desired, and as shown in FIG. 1, the majority decision can be fed back to the register 2 to update the syndrome.
For applications requiring a higher coding gain than can be obtained with hard decisions, "soft" decoding techniques can be employed while retaining the simple structure of the hard decision threshold decoder. Previous applications of soft decisions to digital threshold decoding, such as described in copending application Ser. No. 282,319 filed July 10, 1981, now U.S. Pat. No. 4,404,674 issued Sept. 13, 1983, have resulted in decoder configurations considerably more complex than hard-decision threshold decoders.
An alternative and less complex technique for utilizing probability information present in the received signal is analog threshold decoding of the type described in my prior U.S. Pat. No. 4,130,818. The analog threshold decoder does not require analog-to-digital conversion of the soft demodulator output, but instead utilizes analog shift registers to store the demodulator output directly. The shift register stages are then tapped in the same manner as for hard decision threshold decoding, but analog multiplications of the tapped signals replace the conventional modulo-2 additions, i.e. Exclusive OR operations, and algebraic summation is used in place of the typical majority vote. In this manner, reliability-weighted output estimates are produced directly without the need for intermediate hard-decision decoding as in previous digital techniques.
An improvement in the decoder of U.S. Pat. 4,130,818 is disclosed in my subsequent Pat. No. 4,322,848. As described therein, a reliability weighting can be provided at the input to the decoder to achieve improved performance. A rate one-half systematic convolutional code having a generator polynomial G=1100101 is a self-orthogonal code having a minimum distance of 5 to thereby guarantee the correction of all combinations of two errors in one constraint length with hard decision decoding. The analog threshold decoder of U.S. Pat. No. 4,322,848 for such a code is illustrated in FIG. 2 and utilizes a plurality of tapped analog shift registers 10, 12 and 14 each comprising a charge transfer device of the bucket brigade type. The received analog information (Y) and parity (Z) sequences first undergo a reliability transformation and the reliability-weighted bit streams then enter their corresponding analog shift registers 10 and 12. In addition, the third register 14 stores reliability weighted outputs to permit feedback of previously-decoded output bits.
In place of the Exclusive-OR (EOR) gates of the hard-decision decoder, multipliers 16 form reliability-weighted output estimates composed of the products of various shift register stages. Since each multiplication involves an even number of terms in this case, all multiplier outputs are inverted in forming the summation, so that the output will have a polarity comparable to that which would be achieved with a digital EOR operation, e.g. with a positive signal corresonding to a digital logic "1" and a negative signal corresponding to a digital logic "0". The fifth estimate, since it consists of an odd number of terms, i.e. a single term is not inverted. The summing amplifier forms the average of the five estimates which is then fed to a comparator to form a binary output.
Although the analog threshold decoder shown in FIG. 2 achieved an additional 1.4 dB of coding gain over that achieved by hard-decision threshold decoding with a rate one-half double-error-correcting convolutional code, it is not without its disadvantages. Specifically, since integrated circuit multipliers are available as two-input devices, each of the multipliers 16 shown in FIG. 2 must be formed from a combination of three analog multipliers, thus requiring a total of 12 multipliers for this configuration. Further, this number of multipliers will increase with both higher code rate and longer constraint length.
It would be desirable, therefore, to decrease the number of multipliers required in an analog decoder. Such a reduction would improve the usefulness of the technique for single-channel-per-carrier applications.